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Texas Instruments UCC27200ADDAR — Power Management (PMIC / Gate Driver)

UCC27200ADDAR Half-Bridge Gate Driver, 3A Peak

MPNUCC27200ADDAR
Active

Texas Instruments UCC27200ADDAR, half-bridge gate driver, 3A peak source/sink, 8V-17V supply, 120V bootstrap, 8-PowerSOIC package, -40°C to 140°C junction temp.

$0.9545Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

UCC27200ADDAR specifications
ParameterValue
Gate typeN-Channel MOSFET
Input typeNon-Inverting
Channel typeIndependent
MountingSurface Mount
Supply voltage8V ~ 17V
Logic voltage - VIL, VIH3V, 8V
High side voltage - max (Bootstrap)120 V
Current - peak output (Source, sink)3A, 3A
Operating temperature-40°C ~ 140°C (TJ)
PackageTape & Reel (TR) Cut Tape (CT)
Case8-PowerSOIC (0.154\", 3.90mm Width)
Number of drivers2
Driven configurationHalf-Bridge
Rise (Fall time)8ns, 7ns

Product details

Half-bridge driver for N-channel MOSFETs — 3 A peak, 120 V bootstrap ceiling

It delivers 3 A peak source and sink current with 8 ns rise and 7 ns fall times. The supply range is 8 V to 17 V, so it works on a 12 V bias rail common in industrial and automotive power stages, but not on a 5 V-only bus. The bootstrap pin is rated to 120 V, giving headroom for 48 V, 72 V, or even 100 V DC buses without an external level shifter. The independent channel architecture means the high-side and low-side outputs are not cross-coupled — each has its own non-inverting input, which simplifies dead-time control in firmware or with external logic.

Temperature range and package — fits industrial and under-hood layouts

The 8-PowerSOIC package (0.154" width, 3.90 mm) with an exposed pad is a standard footprint.

No stock-holding claim; the part is procured per the BOM quantity.

Frequently asked questions

Can UCC27200ADDAR be used with N-channel MOSFETs only?

Yes, the gate type is N-channel MOSFET. The half-bridge configuration drives a high-side and a low-side N-channel MOSFET, which is the standard topology for synchronous buck converters and full-bridge inverters.