Package and board-fit constraints
The UA723CDR: The 1.27 mm pitch on a 14-lead SOIC is a standard two-layer board layout — no via-in-pad or microvia needed. Available in Tape & Reel (TR) or Cut Tape (CT) options, so the same reel serves both prototyping and production runs without a packaging change.
Output current and voltage envelope
Rated for 150 mA continuous output, adjustable from 2 V to 37 V via two external resistors — the classic 723 topology that lets a single BOM line cover multiple output rails by swapping the divider. Maximum input voltage is 40 V, so the dropout between input and output must stay within the 723's headroom requirement — typically 3 V for regulation. A 5 V output from a 12 V rail is fine; a 36 V output from a 40 V rail leaves only 4 V headroom, which is marginal under load.
PSRR across the audio band
PSRR is specified at 74 dB to 86 dB over 50 Hz to 10 kHz. At 50 Hz (mains ripple), the 86 dB figure means a 100 mVpp ripple on the input is attenuated to about 5 µVpp at the output — relevant for sensitive analog front-ends running off the same supply. The PSRR declines at higher frequencies; above 10 kHz the internal compensation roll-off reduces rejection, so a local LC filter ahead of the regulator is worth considering if the board carries switching converters.
Built-in current limit and temperature range
The current-limit control feature allows programming the foldback threshold with an external sense resistor — useful for protecting downstream loads during fault conditions without an extra supervisory IC. Not specified for extended industrial or automotive ambient.