What this supervisor does for your rail
The TPS3808G30DBVT is a single-channel voltage supervisor that holds the reset line low whenever the monitored supply drops below 2.79V. The reset output stays asserted for an adjustable timeout period after the supply recovers, giving the downstream processor or FPGA time to stabilize before release. The open-drain output lets you wire-OR multiple supervisors or pull to a different logic level than the monitored rail. The active-low polarity matches the convention used by most MCUs and SoCs.
Setting the reset timeout
A single external capacitor on the CT pin programs the reset delay, which is adjustable from 1.25 ms to 10 s. This is useful when the downstream device needs a specific power-good hold-off — for example, a 100 ms delay for a flash-based MCU to complete its boot sequence. The timeout is set by C_CT = 125 × t_delay (in s), where C_CT is in µF. A 0.1 µF cap gives roughly 12.5 ms; a 1 µF cap gives 125 ms. No resistor needed.