The TPS3307-33DGNR: Both active-high and active-low reset outputs are available from the same device, with a push-pull totem-pole output stage that drives directly into the reset input of an MCU, FPGA, or DSP without an external pull-up resistor.
140 ms reset timeout — what it buys the boot sequence
The 140 ms minimum is a datasheet limit, not a typical value. In a production BOM, the downstream processor's power-on-reset hold time must be shorter than this window, or the supervisor's timeout becomes the limiting factor in the power-up sequence.
The pad is electrically connected to ground — the layout must include thermal vias under the pad to the ground plane.