1.62V threshold supervisor for 1.8V logic rails
The 100ms minimum reset timeout ensures the downstream processor or FPGA sees a stable supply before the reset is released, covering the power-up settling period for most low-voltage cores.
Housed in a SC-74A (SOT-753) package, the part mounts as a standard SOT-23-5 footprint — a common, low-inductance package for board-level voltage monitoring. The small body saves board area on dense mixed-signal PCBs.
This removes the supply-chain risk of a forced redesign mid-production.