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Texas Instruments TPS3124J12DBVR — Power Management (PMIC / Gate Driver)

TPS3124J12DBVR Simple Reset/Power-On Reset IC

MPNTPS3124J12DBVR
Active

Texas Instruments TPS3124J12DBVR Simple Reset/Power-On Reset IC, 1.08V threshold, Active High/Active Low push-pull output, 100ms minimum reset timeout, SOT-23-5 package, -40°C to 85°C.

$1.2225Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

TPS3124J12DBVR specifications
ParameterValue
TypeSimple Reset/Power-On Reset
MountingSurface Mount
Voltage - threshold1.08V
Number of voltages monitored1
Operating temperature-40°C~85°C(TA)
ResetActive High/Active Low
OutputPush-Pull, Totem Pole
PackageTape & Reel (TR); Cut Tape (CT)
Reset timeout100ms Minimum
CaseSC-74A, SOT-753

Product details

1.08V threshold — what it locks onto

The TPS3124J12DBVR: That 1.08V threshold is the trip point — if your core or I/O rail dips under it, the part pulls the reset line low (or high, depending on how you wire the dual outputs) and holds it there for at least 100ms after the rail recovers.

Dual-polarity output — one part, two logic families

Both active-high and active-low reset outputs are available from the same device, with a push-pull, totem-pole stage that drives the line without an external pull-up. If your board has a mix of processors and FPGAs that expect opposite reset polarities, this part covers both without a second BOM line.

SOT-23-5 — field-swappable footprint

Housed in a SOT-23-5 package, surface-mount only. The 5-pin footprint is common enough that you can swap it on site with a standard soldering iron and a steady hand — no hot-air station required.

Frequently asked questions

Is TPS3124J12DBVR active high or active low?

It provides both active-high and active-low reset outputs, giving you flexibility to interface with different logic families without an extra inverter or pull-up.

What is the reset timeout of TPS3124J12DBVR?

The reset timeout is a minimum of 100ms. After the supply rises above the threshold, the reset output stays asserted for at least 100ms before releasing, giving the downstream device time to stabilize.