TPD2EUSB30ADRTR

Texas Instruments

Texas Instruments TPD2EUSB30ADRTR, Steering (Rail to Rail) ESD protection diode array, 2 unidirectional channels, 3.6V reverse standoff, 8V clamping at 1A, 45W peak pulse, -40°C to 85°C, SOT-3 package.

Texas Instruments TPD2EUSB30ADRTR
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MOQ 1 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

TPD2EUSB30ADRTR specifications
Parameter / AttributeSpecification / Value
TypeSteering (Rail to Rail)
MountingSurface Mount
Voltage - breakdown4.5V
Voltage - clamping (Max) @ ipp8V
Voltage - reverse standoff3.6V (Max)
Current - peak pulse (10/1000μs)1A (8/20µs)
Power - peak pulse45W
Power line protectionYes
Operating temperature-40°C~85°C(TA)
PackageTape & Reel (TR); Cut Tape (CT)
ApplicationsGeneral Purpose
Case3-SMD, SOT-23-3 Variant
Unidirectional channels2

Technical details

ESD protection for high-speed differential pairs

The Texas Instruments TPD2EUSB30ADRTR is a steering (rail-to-rail) ESD protection diode array designed to shunt transient overvoltages on two unidirectional signal lines. With a reverse standoff voltage of 3.6V (max) and a clamping voltage of 8V at 1A peak pulse current (8/20µs waveform), it protects downstream ICs on USB 2.0, USB 3.0, HDMI, and other high-speed differential interfaces.

Clamping voltage and signal integrity

The 8V clamping voltage at 1A is the key parameter for design margin: it defines the maximum voltage the protected IC's I/O pins will see during an ESD event. For a USB 3.0 PHY with a 3.6V absolute maximum rating, the 8V clamp leaves 4.4V of headroom — adequate for IEC 61000-4-2 level 4 (±8 kV contact, ±15 kV air) when the diode array is placed close to the connector. The low capacitance typical of steering diodes (not specified here, but inherent to the topology) preserves signal edge rates on 5 Gbps USB 3.0 lanes.

Package and footprint for high-speed layout

Housed in a 3-pin SOT-23-3 variant (SOT-3), this surface-mount device occupies minimal board area and places the protection diodes close to the connector pins — a critical practice for minimizing loop inductance and achieving the rated clamping performance. The small footprint suits space-constrained designs in mobile devices, dongles, and compact I/O modules.

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