It is designed for general-purpose ESD clamping on signal lines up to 9 V reverse standoff, with a peak pulse power rating of 90 W and a maximum clamping voltage of 20 V at 4.5 A (8/20 µs waveform).
For a 9 V standoff line, this translates to roughly 4.5 A of peak current before the clamping voltage rises to 20 V. That clamping voltage is the key number for the downstream IC — if the protected device's absolute-maximum input is, say, 18 V, this part leaves only 2 V of margin. The 0402 footprint forces tight PCB layout: keep the TVS within 5 mm of the connector or ESD entry point to minimise inductive overshoot that can push the actual clamping above the datasheet value.