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Texas Instruments TM4C1292NCZADT3 — Microcontrollers & Processors (MCU / MPU / DSP)

TM4C1292NCZADT3 Tiva C ARM Cortex-M4F MCU, 120 MHz

MPNTM4C1292NCZADT3
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Texas Instruments Tiva™ C TM4C1292NCZADT3, ARM® Cortex®-M4F 32-bit MCU, 120 MHz, 1 MB Flash, 256K x 8 SRAM, 6K x 8 EEPROM, Ethernet/USB OTG/CAN, 140 I/O, 212-NFBGA, -40°C~105°C.

$15.1277Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

TM4C1292NCZADT3 specifications
ParameterValue
SeriesTiva™ C
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))2.97V ~ 3.63V
Operating temperature-40°C~105°C(TA)
Speed120MHz
PackageTray
RAM size256K x 8
Core size32-Bit Single-Core
EEPROM size6K x 8
PeripheralsBrown-out Detect/Reset, DMA, Motion Control PWM, POR, PWM, WDT
ConnectivityCANbus, EBI/EMI, Ethernet, I²C, IrDA, QEI, SPI, SSI, UART/USART, USB OTG
Number of i (O)140
Core processorARM® Cortex®-M4F
Case212-VFBGA
Data convertersA/D 24x12b
Program memory size1MB (1M x 8)

Product details

The TM4C1292NCZADT3: The 140 general-purpose I/O pins and the connectivity block (Ethernet MAC+PHY, USB OTG, two CAN, plus multiple UART/SPI/I²C/SSI interfaces) make this a single-chip candidate for industrial gateways, motor drives with fieldbus, and building-automation controllers that need both wired networking and local sensor aggregation.

The 212-ball NFBGA package measures 10x10 mm — a four-layer PCB with microvias is the practical minimum for routing the 140 I/O and the differential Ethernet pair.

For a production BOM line, this means no forced requalification horizon.

Frequently asked questions

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Is TM4C1292NCZADT3 in stock?

Availability determines lead time and ability to meet production schedules.

Where can I find the TM4C1292NCZADT3 datasheet?

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What is the pinout of TM4C1292NCZADT3?

Pinout accuracy is critical for PCB layout and avoiding costly respins.

Is TM4C1292NCZADT3 obsolete?

Lifecycle status affects long-term availability and risk of redesign for sustainment.