The TM4C1237H6PMI runs an ARM Cortex-M4F core at 80 MHz with a single-cycle multiply and hardware floating-point unit. That clock rate sets the timing budget for the CAN 2.0 and USB OTG interfaces — both are on-chip and share the bus matrix with the 256 KB Flash and 32 KB SRAM. For a control loop reading 12-bit ADC channels and pushing data over CAN, the 80 MHz clock keeps the sample-to-transmit latency under a few microseconds, provided the Flash wait states are configured correctly.
256 KB of Flash and 32 KB SRAM are on-chip. The 2 KB EEPROM stores parameters across reprogramming cycles.
43 I/O and connectivity — what is on the pins
64-LQFP package provides 43 I/O pins. The 12-bit ADC has 12 channels.