TLV803EA26DBZR

Texas Instruments

Texas Instruments TLV803EA26DBZR Simple Reset/Power-On Reset IC, Active Low, Open Drain, 2.64V Threshold, 130ms Timeout, SOT-23-3 Package.

Texas Instruments TLV803EA26DBZR
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MOQ 5 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

TLV803EA26DBZR specifications
Parameter / AttributeSpecification / Value
TypeSimple Reset/Power-On Reset
MountingSurface Mount
Voltage - threshold2.64V
Number of voltages monitored1
Operating temperature-40°C ~ 125°C (TJ)
ResetActive Low
OutputOpen Drain or Open Collector
PackageTape & Reel (TR); Cut Tape (CT)
Reset timeout130ms Minimum
CaseTO-236-3, SC-59, SOT-23-3

Technical details

2.64V threshold — the trip point that decides rail coverage

The TLV803EA26DBZR: The voltage threshold is 2.64V. That number tells you which supply rail this supervisor watches: it sits below a nominal 3.3V rail (which would trigger a reset at about 2.93V for a typical 3.3V supervisor) but above a 2.5V rail. If your design runs a 3.3V core and you need the reset to assert before the logic enters the brownout region, the 2.64V threshold catches the droop early enough to hold the microcontroller in reset while the rail recovers. The 130ms minimum reset timeout holds the output low long enough for the supply to stabilise after power-up — the downstream processor sees a clean release, not a glitch on the reset line as the rail rings.

Open-drain output — wired-OR flexibility with a pull-up cost

The output is open-drain, active low. That means the supervisor can only pull the reset line low; it cannot drive it high. You must add an external pull-up resistor to the logic supply — typically 10 kΩ to 100 kΩ — so that when the reset releases, the line floats high through the resistor. The trade-off is that multiple open-drain outputs (watchdog, other supervisors) can share the same reset line in a wired-OR configuration, which saves a GPIO on the processor.

The SOT-23-3 package has a junction-to-ambient thermal resistance around 200°C/W, so the total dissipation from the pull-up current and the leakage across the open-drain FET stays under the thermal budget across the full range.

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