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Texas Instruments TLV7111833DDSER — Microcontrollers & Processors (MCU / MPU / DSP)

TLV7111833DDSER TI Dual LDO 200mA 1.8V/3.3V, 80dB PSRR

MPNTLV7111833DDSER
End of Life

Texas Instruments TLV7111833DDSER dual LDO regulator, fixed 1.8V and 3.3V outputs, 200mA per channel, 80dB PSRR, 6-WSON (1.5x1.5) package, surface mount.

$0.72Ref. price · indicative, final on quote
Packaging6-WFDFN
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

TLV7111833DDSER specifications
ParameterValue
Output typeFixed
MountingSurface Mount
Voltage - input5.5V
Voltage dropout-, 0.2V @ 200mA
Voltage - output (Min (Fixed))1.8V, 3.3V
Output current200mA
Current - quiescent110 µA
Operating temperature-40°C ~ 125°C (TJ)
PSRR80dB ~ 50dB (10Hz ~ 100kHz)
PackageTape & Reel (TR); Cut Tape (CT)
Case6-WFDFN
Control featuresEnable
Protection featuresOver Current, Over Temperature, Short Circuit, Under Voltage Lockout (UVLO)
Number of regulators2
Output configurationPositive

Product details

Dual-rail LDO for mixed-signal noise budgets

The TLV7111833DDSER: This pair matches the common core-and-I/O voltage split for a small MCU or mixed-signal IC — one LDO powers the digital core, the other the analog or GPIO supply, sharing a single input capacitor and enable pin. The PSRR profile — 80 dB at 10 Hz rolling off to 50 dB at 100 kHz — tells you where this regulator earns its keep. At audio-band frequencies the rejection is high enough to keep switching-ripple from a preceding buck converter off a sensitive ADC reference or audio codec supply. Above 100 kHz the rejection drops, so the upstream filter design matters if your noise spectrum peaks in the hundreds of kilohertz.

Dropout, quiescent, and protection — the operating envelope

Maximum dropout on the 3.3 V output is 0.2 V at 200 mA load. That means the input rail must stay above 3.5 V to maintain regulation at full current — a 3.6 V lithium cell near end-of-discharge is marginal; a 5 V rail has comfortable headroom. Protection features cover overcurrent, overtemperature, short-circuit, and undervoltage lockout. The UVLO threshold keeps the outputs off until the input rail is high enough to regulate cleanly — prevents brownout glitches during power-up sequencing. The thermal shutdown threshold is not specified in the brief, but the -40 to +125 °C junction-temperature range means the die can operate in an engine bay or hot enclosure as long as the board-level thermal resistance stays within the package's dissipation limits.

The 6-WSON (1.5x1.5 mm) with exposed thermal pad demands a PCB layout that treats the pad as the primary heat path. Without that thermal connection, the junction temperature rises faster than the 200 mA per channel rating suggests, especially when both LDOs are loaded simultaneously in a warm ambient. The enable pin lets the system power down one or both rails without dropping the input — useful for sequencing or sleep-mode power gating.

Lifecycle and compliance status

ROHS3 compliant, so it meets the current EU exemption-free standard. No official successor or pin-compatible alternate is documented; the part is the current design-in choice for this dual-rail fixed-voltage combination.

Frequently asked questions

What is the PSRR of the TLV7111833DDSER and why does it matter?

PSRR is 80 dB at 10 Hz, rolling to 50 dB at 100 kHz. That means the regulator attenuates ripple on the input by a factor of 10,000 at low frequencies — critical for keeping switching noise from a preceding DC-DC converter off a sensitive analog supply rail. Above 100 kHz the rejection is lower, so the upstream filter design must handle the high-frequency content.