Dual 12-bit DAC with a wide temperature span
The TLV5618AQD: It uses a String DAC architecture with a buffered voltage output, an SPI data interface, and requires an external voltage reference.
10 µs settling — what it buys the loop
The 10 µs settling time to ±0.5 LSB (the DNL spec) sets a practical update ceiling around 100 kHz for a full-scale step. In a closed-loop valve or motor-current control path, that settling window defines the minimum loop period — the DAC output must be stable before the ADC samples the feedback. The dual channels let one DAC hold a setpoint while the other updates, eliminating the dead time a single-channel part would impose.
Supply rails and reference — no surprises
The external reference sets the full-scale output. The 8-SOIC footprint (3.90 mm width) fits a 2-layer board with a solid ground pour under the package.