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TLV5618ACDG4

TLV5618ACDG4 Dual 12-Bit DAC, 10 µs Settling, SPI

MPNTLV5618ACDG4
End of Life

Texas Instruments TLV5618ACDG4, dual 12-bit voltage-output DAC, 10 µs settling time, SPI interface, ±2 LSB INL, 8-SOIC package, 0°C to 70°C.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

TLV5618ACDG4 specifications
ParameterValue
Output typeVoltage - Buffered
MountingSurface Mount
Reference typeExternal
Voltage - supply, analog2.7V ~ 3.3V, 5V
Voltage - supply, digital2.7V ~ 3.3V, 5V
Data interfaceSPI
Operating temperature0°C~70°C
PackageTube
ArchitectureString DAC
INL (DNL)±2, ±0.5
Settling time10µs
Number of bits12
Case8-SOIC (0.154\", 3.90mm Width)
Differential outputNo
Number of d (A converters)2

Product details

Dual 12-bit DAC in an 8-pin SOIC

It integrates two independent DACs with a buffered voltage output, each settling to within 1 LSB in 10 µs. The SPI-compatible serial interface controls both channels over a single data line, making it a compact fit for industrial control loops, programmable voltage references, and waveform generation where board area is tight.

Settling time and linearity budget

The 10 µs settling time to 1 LSB sets the maximum update rate at roughly 100 kHz for a full-scale step — fast enough for most closed-loop process control and audio-frequency signal generation. The ±2 LSB integral nonlinearity (INL) and ±0.5 LSB differential nonlinearity (DNL) define the analog output accuracy. For a 12-bit converter with a 5 V reference, ±2 LSB INL corresponds to a potential error of about 2.4 mV at the output; the ±0.5 LSB DNL guarantees monotonicity, which matters when the DAC drives a servo valve or a trim pot where a non-monotonic step would cause a control reversal.

Supply range and reference

The reference voltage is supplied externally — the output full-scale equals twice the reference voltage. This lets the designer set the output span independently of the supply, useful when the DAC drives an ADC with a different reference voltage or a sensor bridge that needs a precise 0-to-2.5 V range.

Production status and ordering

The 8-SOIC package ships in Tube form.

Frequently asked questions

What is the settling time of TLV5618ACDG4?

The settling time is 10 µs to within 1 LSB for a full-scale step. This sets a practical update rate of about 100 kHz for large output swings; smaller step changes settle faster.

Does TLV5618ACDG4 support SPI interface?

Yes, the data interface is SPI-compatible. A single serial data line clocks in the 12-bit data and channel-select bits, controlled by a chip-select and serial clock.

What is the output type of TLV5618ACDG4?

The output type is Voltage - Buffered. Each of the two DAC channels has an internal buffer amplifier that can drive resistive loads directly without an external op-amp.