J-FET input stage — 65 pA bias current
The J-FET input stage delivers a typical input bias current of 65 pA, which keeps the DC error low when the op-amp is driven from a high-impedance source such as a photodiode or a piezoelectric sensor. The 3 mV input offset voltage is the untrimmed grade — for precision DC-coupled circuits, the TL072AC (3 mV max) is the tighter bin versus the standard TL072 (6 mV).
13V/µs slew rate — signal-chain headroom
A 13V/µs slew rate with a 3 MHz gain-bandwidth product means the amplifier can swing a 10 Vpp sine wave up to about 200 kHz before the output slew-rate limits the amplitude. This is adequate for audio processing, active filters, and general-purpose signal conditioning in the 20 Hz–100 kHz band.