J-FET input stage — what it buys you
The TL071ACD is a single J-FET input op-amp from STMicroelectronics, part of the TL071 family. The J-FET front end gives it a 65 pA input bias current, which keeps offset errors low when the source impedance is high — think photodiode transimpedance or piezo sensor conditioning.
Slew rate and bandwidth for signal chains
Rated 13V/µs slew rate with a 5.25 MHz gain-bandwidth product. Supply current is 1.4 mA typical, running from a single or split supply spanning 10 V to 30 V total. The 3 mV input offset voltage (max) is adequate for general-purpose analog processing, though a precision-grade sibling would be tighter for microvolt-level work.
Obsolete — plan the replacement now
Confirm the offset and temperature grade against your BOM before committing.
Package and storage notes
Supplied in Tube (standard 8-SOIC, 0.154-inch body width). Surface-mount reflow profile per JEDEC MSL-1 — no dry-bake required if the seal is intact. Store the tubes in a clean, dry bin; the SOIC leads are tin-plated and corrosion-resistant, but humidity cycling can dull the solderability over long shelf life.