Quad LVDS receiver for 3.3 V backplane and cable links
It is designed for point-to-point or multidrop serial links running at up to 155 Mbps per channel, common in telecom backplanes, base station clock distribution, and video data recovery over twisted-pair or PCB traces.
Each of the four receivers handles a 155 Mbps serial stream, which is the SONET OC-3 / SDH STM-1 line rate. In practice that means the part can recover a 77 MHz clock from a 155 Mbps NRZ data stream with adequate setup-and-hold margin for a downstream deserialiser or FPGA LVDS input. If your link runs slower – say 100 Mbps Ethernet or a 50 MHz pixel clock – the SN75LVDS32DR has headroom to spare; the limiting factor becomes the input common-mode range and the cable length, not the data rate.
Supply rail and temperature – indoor 3.3 V logic only
It is not tolerant of 5 V or 2.5 V logic without level translation on the CMOS outputs.