Parametric fit — timing, drive, and supply rails
The SN74LVTH373PWR: Propagation delay is 2.7 ns typical — at a 100 MHz bus cycle (10 ns period), the latch adds under 3 % of the cycle budget, leaving margin for clock skew and trace delay. Output drive is 32 mA source, 64 mA sink — the asymmetric sink strength handles capacitive loads on the data bus without an external buffer, though the 32 mA source limits fan-out to five 74LVTH inputs (each drawing 5 µA typ).
Package and temperature grade for board integration
Surface-mount reflow profile follows JEDEC MSL-1 (moisture sensitivity level not stated, but the package is standard for this class).