Dual 8-bit D-type — 160 MHz bus register
It clocks at 160 MHz, operates from 2.7 V to 3.6 V, and drives 32 mA source / 64 mA sink per output.
160 MHz clock — timing margin on a shared bus
The 160 MHz clock rate and 4.5 ns propagation delay at 3.3 V, 50 pF give the designer a clean timing budget for address/data latching in high-throughput memory-mapped or DMA paths. The 3 pF input capacitance keeps the clock-line loading light, which matters when multiple flip-flops share a single clock tree on a dense PCB.
The SN74LVTH16374DGGR is an active, current-production part (ROHS3 compliant).