Dual 8-bit register for mixed-voltage buses
It belongs to the 74LVCH family and operates across a 1.65 V to 3.6 V supply range.
Clock frequency and propagation delay — timing budget
Rated at 150 MHz clock frequency, this register meets the timing needs of DDR memory controllers and high-speed parallel buses. The 4.5 ns max propagation delay at 3.3 V with 50 pF load gives the designer a clear window for setup-and-hold closure on the receiving side.
Output drive and quiescent current
Each output can source or sink 24 mA, symmetrical. Quiescent current sits at 20 µA, keeping standby power low in battery-backed or always-on subsystems. Input capacitance is 5 pF, light enough to not load the driving bus excessively.
The 48-TSSOP footprint is common on multi-layer boards; the 0.240" body width fits standard SOIC-width land patterns.
ROHS3 compliant — no exemption expiry concern for EU or global markets.