4.4 ns propagation delay — timing budget for fast buses
The 4.4 ns maximum propagation delay at 3.3V and 50 pF load keeps signal skew tight in clocked systems. For comparison, the NAND-gate sibling SN74LVC10AD lists 4.7 ns under the same conditions — the XOR gate is slightly faster, which matters when the gate sits in a critical path like a data bus comparator or a clock-phase detector. At 1.8V the delay is longer, but the 74LVC family is characterised across the full supply range, so timing closure tools can use the datasheet curves directly.