Dual D-type with set/reset — 150 MHz in a 14-SOIC
Each of the two elements stores one bit, clocked at up to 150 MHz. The 1.65 V to 3.6 V supply range lets it bridge 1.8 V, 2.5 V, and 3.3 V logic domains without a level shifter — useful in mixed-voltage boards where a single logic family must talk to both a low-voltage MCU and a legacy 3.3 V peripheral.
5.2 ns propagation delay — timing budget for the bus
At 3.3 V with a 50 pF load, the max propagation delay is 5.2 ns. That is the number to enter into your timing closure spreadsheet for the data-to-clock path. The 24 mA symmetric output drive (both high and low) keeps edge rates fast enough to meet setup times on downstream loads without extra buffering. Input capacitance is 5 pF, so fanout on a 3.3 V bus is manageable — figure 10 to 15 loads before the rise time degrades.
The quiescent current sits at only 10 µA, so it adds negligible draw to a battery-backed or always-on rail.