SN74LVC2G32DCUR

Texas Instruments · 74LVC Series

Texas Instruments 74LVC series SN74LVC2G32DCUR, dual 2-input OR gate, 1.65V to 5.5V supply, 32mA output drive, 3.2ns propagation delay at 5V/50pF, -40°C to 125°C, 8-VSSOP package.

Texas Instruments SN74LVC2G32DCUR
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MOQ 1 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

SN74LVC2G32DCUR specifications
Parameter / AttributeSpecification / Value
Series74LVC
Logic typeOR Gate
MountingSurface Mount
Supply voltage1.65V ~ 5.5V
Current - quiescent10 µA
Current - output high, low32mA, 32mA
I/O channels2
Operating temperature-40°C ~ 125°C
PackageTape & Reel (TR); Cut Tape (CT)
Case8-VFSOP (0.091\", 2.30mm Width)
Number of circuits2
Input logic level - low0.7V ~ 0.8V
Input logic level - high1.7V ~ 2V
Max propagation delay @ v, max CL3.2ns @ 5V, 50pF

Technical details

A dual OR gate for mixed-voltage boards

It operates from 1.65V to 5.5V, making it a natural fit for boards that mix 1.8V, 2.5V, 3.3V, and 5V logic domains. Each of the two gates can source or sink 32mA, and the propagation delay is 3.2ns at 5V with a 50pF load.

The wide supply range means this gate can be powered from the same rail as a 1.8V MCU or a 5V PLC input module. The input logic levels scale with supply: low-level threshold is 0.7V to 0.8V, high-level is 1.7V to 2V. At 3.3V the thresholds sit around 0.8V and 1.7V, giving about 0.9V of noise margin on each edge. That's comfortable for most backplane and cable interfaces.

Output drive and speed

With 32mA output drive per channel, this gate can directly drive a MOSFET gate through a series resistor, or fan out to four or five standard CMOS loads. The 3.2ns propagation delay at 5V is fast enough for 50-100 MHz clock distribution or address decoding without adding a full clock cycle of skew. At 3.3V the delay will be slightly higher, typically around 4-5ns, but still fine for most glue-logic tasks.

It is ROHS3 compliant.

SN74LVC2G32DCUR
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