The inverted output saves an external inverter when the downstream logic expects the complement of the stored bit. Quiescent current is just 10 µA, so it adds negligible overhead to a power budget even in always-on sections of a design.
160 MHz clock — timing margin for high-speed buses
The 160 MHz maximum clock frequency means the flip-flop can register data in fast serial or parallel buses with a 6.25 ns period. Propagation delay is 4.5 ns at 5 V with a 50 pF load, which sets the minimum setup-and-hold window the driving logic must meet. At lower supply voltages the delay increases — budget accordingly when running at 1.8 V. Output drive is symmetric at 32 mA source and sink, enough to switch a high-speed bus line or drive a small indicator LED without a buffer. Input capacitance is 3.5 pF, light enough not to load the preceding gate's fan-out.
If you need a dual-source hedge, the 74LVC1G80 is available from multiple manufacturers in the same SC-70-5 footprint — confirm the exact suffix for tape-and-reel orientation.
SC-70-5 package — board fit
Housed in a 5-lead SC-70 (SOT-353) package, the part occupies roughly 2 mm × 2.1 mm of board area.