Skip to main content
Texas Instruments SN74LVC1G79DCKT — Logic ICs

SN74LVC1G79DCKT D-Type Flip-Flop, 160 MHz, SC-70-5

MPNSN74LVC1G79DCKT
Active

Texas Instruments 74LVC family SN74LVC1G79DCKT, single D-type flip-flop, positive-edge triggered, non-inverted output, 160 MHz clock frequency, 1.65 V to 5.5 V supply, 4.5 ns propagation delay at 5 V/50 pF, -40°C to 125°C, SC-70-5 package.

$0.9400Ref. price · indicative, final on quote
Packaging5-TSSOP, SC-70-5, SOT-353
RoHSROHS3 Compliant
Series74LVC
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74LVC1G79DCKT specifications
ParameterValue
TypeD-Type
Series74LVC
Output typeNon-Inverted
Trigger typePositive Edge
MountingSurface Mount
Supply voltage1.65V ~ 5.5V
Current - quiescent10 µA
Current - output high, low32mA, 32mA
Clock frequency160 MHz
Operating temperature-40°C~125°C(TA)
PackageTape & Reel (TR); Cut Tape (CT)
FunctionStandard
Case5-TSSOP, SC-70-5, SOT-353
Input capacitance4 pF
Number of elements1
Number of bits per element1
Max propagation delay @ v, max CL4.5ns @ 5V, 50pF

Product details

Single-bit D-type flip-flop for high-speed bus isolation

It stores one data bit and presents a non-inverted output on the rising edge of the clock. Clock frequency is rated at 160 MHz, with a maximum propagation delay of 4.5 ns at 5 V into a 50 pF load. Output drive capability is ±32 mA, enough to feed a standard CMOS input or drive a small LED without an external buffer. Quiescent current is 10 µA, keeping the standing power low in battery-powered equipment. The SC-70-5 package (2.0 mm × 2.1 mm body) fits into dense PCB layouts where board area is at a premium.

Supply voltage range and mixed-voltage interface

One flip-flop variant can serve as a level translator between a 1.8 V microcontroller GPIO and a 3.3 V sensor, or between a 3.3 V FPGA and a 5 V legacy backplane. The input thresholds track VCC, so at 1.8 V the VIH is about 1.26 V; at 5 V it is 3.5 V. Input capacitance is 4 pF, which keeps the loading light on the driving node even when multiple flip-flops are paralleled on a shared clock line. The positive-edge trigger simplifies timing analysis because the setup and hold windows are referenced to the rising edge only.

Propagation delay and timing closure

The 4.5 ns max propagation delay at 5 V is the number to budget for worst-case timing. If the clock-to-Q delay of the driving flip-flop is 3 ns and the SN74LVC1G79DCKT adds 4.5 ns, the receiving register must have a setup time greater than 7.5 ns to avoid a metastability window. At 160 MHz the clock period is 6.25 ns, so this part is best used in one- or two-gate delay paths rather than deep pipelines at full frequency. For lower-speed clocks the margin is generous.

Package and footprint for dense layouts

The SC-70-5 package (also known as SOT-353) has a 2.0 mm × 2.1 mm footprint with 0.65 mm pin pitch. It is one of the smallest packages for a single-gate logic function. The five pins are VCC, GND, D, CLK, and Q. The small body means the decoupling capacitor must be placed close — a 0.1 µF ceramic in 0402 or 0201 size fits directly adjacent. No thermal pad is needed; the package dissipates through the leads and the small epoxy body.

ROHS3 compliance is confirmed.

Frequently asked questions

Is SN74LVC1G79DCKT a direct replacement for SN74LVC1G79DBVT?

Both parts share the same base number 74LVC1G79 and identical electrical specifications. The difference is the package: DCKT is SC-70-5 (Tape & Reel), DBVT is SOT-23-5 (Cut Tape). They are not footprint-compatible; verify the PCB land pattern before substituting.

Is SN74LVC1G79DCKT RoHS compliant?

Yes, it is ROHS3 compliant.