Single 3-input OR gate in a 1x1 mm SON
Propagation delay is 4.5 ns at 5 V with a 50 pF load, which keeps timing margin clean in mixed-voltage datapaths.
Wide supply and extended temperature
The 1.65 V minimum supply means it can run straight off a 1.8 V rail without a level translator. Input logic thresholds are specified at 0.7 V to 0.8 V for low and 1.7 V to 2 V for high, which is compatible with 1.8 V CMOS and 3.3 V LVCMOS families alike. Quiescent current maxes at 10 µA, so it won't eat into a battery budget.
Production status and compliance
It is ROHS3 compliant, which means no exemption-limited substances in the bill of materials.