SN74LVC1G32QDRYRQ1

Texas Instruments · Automotive, AEC-Q100, 74LVC Series

Texas Instruments SN74LVC1G32QDRYRQ1, Automotive AEC-Q100 74LVC series, single 2-input OR gate, 1.65 V to 5.5 V supply, 32 mA output drive, 4.5 ns propagation delay at 5 V/50 pF, -40°C to 125°C, 6-UFDFN package.

Texas Instruments SN74LVC1G32QDRYRQ1
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[IN STOCK] In Stock: 32 pcs
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MOQ 1 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

SN74LVC1G32QDRYRQ1 specifications
Parameter / AttributeSpecification / Value
SeriesAutomotive, AEC-Q100, 74LVC
Logic typeOR Gate
MountingSurface Mount
Supply voltage1.65V ~ 5.5V
Current - quiescent10 µA
Current - output high, low32mA, 32mA
I/O channels2
Operating temperature-40°C~125°C
PackageTape & Reel (TR); Cut Tape (CT)
Case6-UFDFN
Number of circuits1
Input logic level - low0.7V ~ 0.8V
Input logic level - high1.7V ~ 2V
Max propagation delay @ v, max CL4.5ns @ 5V, 50pF

Technical details

Qualified for the underhood, sized for the tight spot

That means it is not an industrial part being marketed as 'automotive-capable' — it carries the grade documentation an OEM auditor expects to see in a PPAP package. Output drive is 32 mA per pin, enough to switch a small relay coil or drive a signal through a long harness segment. The propagation delay of 4.5 ns at 5 V and 50 pF keeps it in budget for CAN transceiver enable signals and sensor interrupt paths running at a few MHz.

Package reality: 6-UFDFN, not a through-hole part

This is a surface-mount device in a 6-UFDFN package (the supplier device package is 6-SON, 1.45 mm x 1.0 mm per the base number family). That footprint is tiny — about the size of a 0402 resistor — so the PCB layout needs a well-defined solder-paste aperture and a stencil design that does not bridge the narrow pitch. There is no exposed thermal pad to worry about; the quiescent current is only 10 µA max, so self-heating is negligible even at 125°C ambient.

That makes it a safe choice for a new BOM line that will run for several years. There is no risk of a sudden discontinuation mid-program.

What the 4.5 ns propagation delay means for your bus

The 4.5 ns figure is specified at 5 V supply and 50 pF load, which is a standard test condition. In a real 3.3 V system with a 15 pF gate load (one or two downstream inputs), the delay will be shorter — typically in the 2.5 ns to 3.5 ns range. If you are clocking a signal at 10 MHz or higher, budget the delay against the set-up time of the receiving flip-flop; the 74LVC family has tight output-edge rates that help keep the timing margin healthy.

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