Single-gate buffer for mixed-voltage buses
The SN74LVC1G126DCKR is a single non-inverting buffer with 3-state output.
At 1.8V it interfaces directly with low-voltage ASICs or FPGAs; at 3.3V or 5V it matches legacy logic. No external level translator is needed when the buffer's supply matches the downstream rail. The 32 mA symmetrical drive at both logic levels keeps rise and fall times balanced, which simplifies timing closure on a shared bus. If the load exceeds 32 mA per pin, buffer the output with a discrete transistor or use a higher-drive gate.
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