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Texas Instruments SN74LVC1G10DSFR — Logic ICs

SN74LVC1G10DSFR 74LVC NAND Gate, 1.65V-5.5V, 6SON

MPNSN74LVC1G10DSFR
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Texas Instruments 74LVC series SN74LVC1G10DSFR, single 3-input NAND gate, 1.65V to 5.5V supply, 32mA output drive, 3.6ns propagation delay at 5V/50pF, -40°C to 125°C, 6-SON (1x1mm) package.

$0.5300Ref. price · indicative, final on quote
Packaging6-XFDFN
RoHSROHS3 Compliant
Series74LVC
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74LVC1G10DSFR specifications
ParameterValue
Series74LVC
Logic typeNAND Gate
MountingSurface Mount
Supply voltage1.65V ~ 5.5V
Current - quiescent10 µA
Current - output high, low32mA, 32mA
I/O channels3
Operating temperature-40°C~125°C
PackageTape & Reel (TR); Cut Tape (CT)
Case6-XFDFN
Number of circuits1
Input logic level - low0.7V ~ 0.8V
Input logic level - high1.7V ~ 2V
Max propagation delay @ v, max CL3.6ns @ 5V, 50pF

Product details

Single 3-input NAND gate in a 1x1mm SON

The device sinks or sources 32mA per output, enough to drive a small LED or a downstream gate input directly. Propagation delay is rated at 3.6ns maximum at 5V with a 50pF load, keeping the timing budget tight for high-speed glue logic.

Supply voltage and 1.8V compatibility

The 1.65V minimum supply means this gate works cleanly on a 1.8V rail. Input logic thresholds are specified as 0.7V to 0.8V for low and 1.7V to 2V for high across the full supply range, so it interprets 1.8V CMOS levels correctly. No separate translator needed when bridging a 1.8V controller to a 3.3V peripheral.

The 6-SON (1x1mm) footprint is about the size of a 0402 resistor — critical for dense PCBs where every mm² counts. Surface-mount only, no through-hole variant. The small pad pitch means solder paste inspection and a clean reflow profile matter;.

No NRND or EOL flags. No last-time-buy or end-of-life scheduling to track.

Frequently asked questions

Is SN74LVC1G10DSFR compatible with 1.8V logic?

Yes. The supply voltage range starts at 1.65V, and the input logic thresholds (low: 0.7V to 0.8V, high: 1.7V to 2V) are designed to accept 1.8V CMOS levels without additional translation.