Quad buffer with 3-state outputs in 14-SOIC
The SN74LVC126ADR is a quad non-inverting buffer from TI's 74LVC series, each channel independently gated by a 3-state output enable.
24 mA output drive at industrial temperature
Each buffer sinks or sources 24 mA in both high and low states, enough to drive a standard CMOS load or a short backplane trace without an external line driver. The 3-state output architecture lets multiple buffers share a common data bus — the output goes high-impedance when the enable pin is low, preventing bus contention in multiplexed memory address or data lines.