Active dual JK flip-flop for mixed-voltage logic chains
The SN74LVC112APW: The 150 MHz maximum clock frequency handles fast counter chains, shift registers, and frequency dividers where timing margin matters.
5.9 ns propagation delay and 24 mA output drive
Max propagation delay is 5.9 ns at 3.3V with a 50 pF load — that sets the data-to-output settling time in a clocked path. For a 150 MHz clock (6.67 ns period), the delay consumes about 88% of the cycle, leaving roughly 0.77 ns of setup/hold margin before the next edge. In slower 1.8V operation the delay will be longer, so budget accordingly at the lower supply rail. Each output sources or sinks 24 mA, enough to drive multiple CMOS loads or a short PCB trace without a buffer. Input capacitance is 4.5 pF typical, so fan-out calculations should include this loading per driven gate. Quiescent current sits at 10 µA typical — negligible for battery-powered designs where the flip-flop stays clocked but idle between events.