Triple 3-input NAND in a 14-TSSOP footprint
The SN74LVC10APW is a triple 3-input NAND gate from Texas Instruments' 74LVC logic family, packaged in a 14-TSSOP (4.40mm width) surface-mount package. Each of the three independent NAND gates accepts three inputs and delivers a standard 24mA output drive (both source and sink), enough to fan out to multiple CMOS loads or drive a single TTL input directly.
Propagation delay and signal timing
Maximum propagation delay is 4.7ns at 3.3V with a 50pF load — this sets the data-rate ceiling for a clean signal path. At 1.8V the delay increases, so the actual toggle rate at the receiver is lower than the bare 4.7ns suggests; budget this into timing closure for fast parallel buses. Quiescent current draws just 1 µA maximum, so the gate adds negligible standby power in battery-operated designs. The input logic thresholds are specified as 0.7V–0.8V for low and 1.7V–2V for high, ensuring reliable switching across the full supply range.
The 14-TSSOP package with 0.65mm pitch demands a standard surface-mount assembly process — no special via-in-pad or thermal management required for this low-power CMOS device.