Triple 3-input NAND in the 74LVC family
The SN74LVC10ANSR: Three independent NAND gates, each with three inputs, are packaged in a 14-pin SOIC (0.209-inch body width, 5.30 mm) — the 14-SO footprint that mates with standard SOIC-14 land patterns. The supplier device package is designated 14-SO.
Supply voltage and temperature envelope
The input logic thresholds scale with VCC: low-level threshold is 0.7 V to 0.8 V, high-level threshold is 1.7 V to 2 V — so at 3.3 V VCC, a 1.8 V CMOS signal is still recognised as a logic high.
Speed and drive at 3.3 V
Maximum propagation delay is 4.7 ns at 3.3 V with a 50 pF load — this sets the data-rate ceiling for a single gate in a signal path. The 24 mA symmetric output drive (source and sink) can switch the 50 pF load with edge rates fast enough for 100+ MHz clock distribution in a point-to-point topology. Quiescent current is 1 µA max — the gates draw virtually no DC current when the inputs are static, which matters for battery-powered or power-sensitive designs where the logic sits idle most of the time.