Quad AND gate in the 74LVC family — 3.9ns at 3.3V
The SN74LVC08AD is a quad 2-input AND gate from the 74LVC series, packaged in a 14-SOIC (0.154", 3.90mm width) surface-mount tube. Maximum propagation delay is 3.9ns at 3.3V with a 50pF load — that 3.9ns figure sets the timing budget for the critical path in a 100+ MHz synchronous bus. At lower supply voltages the delay increases; budget 6–7 ns at 1.8V if you need the same fan-out.
24 mA output drive and 1 µA quiescent draw
Each output sources or sinks 24 mA — enough to drive three or four standard 74LVC inputs directly or a low-power LED indicator without a buffer. Input logic thresholds are specified at 0.7V–0.8V (low) and 1.7V–2V (high) across the supply range — the 0.8V low threshold at 3.3V gives 0.4V of noise margin below ground-referenced 1.2V logic, so a 1.2V output from an adjacent FPGA pin is recognised as a valid low without a pull-down resistor.
Industrial temperature grade and compliance
The 125°C ceiling means the gate can sit next to a hot regulator or on a board near an engine bay without derating the output drive. Lifecycle status is Active and the part is ROHS3 compliant.