TI 74LV series, SN74LV132ADR, quad 2-input NAND gate with Schmitt-trigger inputs, 2V-5.5V supply, 12 mA output, 9.7 ns propagation delay at 5V/50pF, -40 to 125°C, 14-SOIC.
| Parameter | Value |
|---|---|
| Series | 74LV |
| Logic type | NAND Gate |
| Mounting type | Surface Mount |
| Voltage | 2V ~ 5.5V |
| Current - quiescent | 20 µA |
| Current - output high, low | 12mA, 12mA |
| Number of inputs | 2 |
| Operating temperature | -40°C ~ 125°C (TA) |
| Package | Tape & Reel (TR); Cut Tape (CT) |
| Features | Schmitt Trigger |
| Case | 14-SOIC (0.154\", 3.90mm Width) |
| Number of circuits | 4 |
| Input logic level - low | 0.75V ~ 1.5V |
| Input logic level - high | 1.75V ~ 3.5V |
| Max propagation delay @ v, max CL | 9.7ns @ 5V, 50pF |
The TI SN74LV132ADR is a quad 2-input NAND gate from the 74LV series, with Schmitt-trigger inputs on all four gates. It operates from 2V to 5.5V supply.
Maximum propagation delay is 9.7 ns at 5V with a 50 pF load.
The SN74LV132ADR is supplied in a 14-pin SOIC package (body width 3.90 mm), surface-mount. TI lists the part as Active and ROHS3 compliant.
The closest functional equivalent within the 74LV series is the SN74LV00APWR, which is also a quad 2-input NAND gate but without Schmitt-trigger inputs. The SN74LV132ADR's Schmitt-trigger hysteresis is the key differentiator — it handles slow or noisy edges that a standard NAND gate would pass through as indeterminate logic levels. If you do not need the Schmitt-trigger, the SN74LV00APWR is a pin-compatible drop-in. For a Schmitt-trigger NAND in a different logic family, the SN74HC132 is a common alternative, but verify the supply voltage and timing differences.
Yes, in many cases. Both are quad 2-input NAND gates with Schmitt-trigger inputs in the same 14-SOIC footprint. The key difference is the supply range: the LV version operates from 2V to 5.5V, while the HC version is typically specified from 2V to 6V. The LV part has lower quiescent current (20 µA max vs roughly 80 µA for HC) and faster propagation delay at 5V (9.7 ns vs roughly 15 ns for HC). Verify the input logic levels match your driving stage — the LV series has different VIH/VIL thresholds than HC.
Yes. The supply voltage range of 2V to 5.5V includes 5V operation. At 5V, the propagation delay is 9.7 ns with a 50 pF load, and the output can sink or source 12 mA. The input logic levels at 5V are 0.75V to 1.5V for low and 1.75V to 3.5V for high, which are compatible with 5V CMOS and TTL families.