Quad non-inverting buffer with 3-state outputs — 74LV family
It operates across a 2V to 5.5V supply range, making it usable on legacy 5V TTL buses and modern 3.3V or 2.5V logic rails alike. The 16mA symmetric source and sink drive is typical for this logic family — enough to drive a few CMOS inputs or a short PCB trace without needing a separate line driver. The 14-SOIC package (0.209", 5.30mm width) is a common footprint that routes easily on two-layer boards and reworks without hot-air stations.
Supply voltage flexibility — 2V to 5.5V
The 2V to 5.5V supply range is the headline selection parameter for this buffer. If your board has a 3.3V main rail and a 5V peripheral bus, this part bridges them without a level translator, as long as the input thresholds align. At 3.3V the 74LV family switches fast enough for most SPI and UART buses below 20 MHz; at 5V it meets TTL thresholds directly. The wide range also absorbs supply droop — a 3.3V rail that sags to 2.8V during a load transient still keeps the buffer operational.
3-state bus control
Each of the four buffers has its own output-enable pin, so you can gate individual signals onto a shared bus without external AND-OR logic. The 3-state output goes high-impedance when the enable is low, letting another driver take the line. This is the standard architecture for address/data bus buffers in microcontroller memory expansion or for multiplexing sensor outputs onto a single ADC input channel.