Triple 3-input NAND gate for mixed-voltage logic
The Texas Instruments SN74LV10APW is a triple 3-input NAND gate from the 74LV low-voltage logic family. Each of the three independent gates can sink or source 12mA, and the propagation delay is 7.9ns at 5V with a 50pF load — fast enough for most 10-20 MHz bus applications without the power penalty of the 74LVC family.
The 2V to 5.5V supply range is the headline selection parameter. At 3.3V the gate still switches cleanly with the same 12mA output drive, so you can use it as a level translator without a dedicated translator IC — the input thresholds (0.5V low, 1.5V high) are fixed relative to VCC, not ratiometric, which means a 3.3V-powered gate will correctly interpret a 5V TTL signal as high. The 7.9ns propagation delay at 5V is the worst-case number across temperature and voltage; at 3.3V you can expect roughly 11-12ns, still adequate for SPI clock rates up to 20 MHz. If your bus runs faster than that, the 74LVC10AD offers 4.7ns at 3.3V but is limited to a 3.6V supply ceiling.
The 14-TSSOP footprint is shared with other 74LV and 74LVC triple-gate parts, so a layout can be reused across the family.
The closest functional peer is the SN74LVC10AD, which offers higher speed and a wider temperature range but requires a 1.65V to 3.6V supply.