Open-drain hex inverter for mixed-voltage buses
The SN74LV05ANS packs six independent inverter gates with open-drain outputs in a 14-SOIC package. Each channel accepts a single input and drives the output low when the input is high; when the input goes low, the output floats, letting an external pull-up resistor define the high-level voltage. The supplier device package is 14-SO, which is the same mechanical outline as the standard SOIC-14.
Supply range, temperature grade, and power budget
Runs on any supply from 2V to 5.5V, which covers the full 3.3V and 5V logic families plus the lower 2.5V and 1.8V rails used in battery-powered designs. Quiescent current maxes at 20 µA across the whole temperature range. For a six-gate device that is roughly 3.3 µA per gate — negligible in a battery budget, and the open-drain outputs draw no additional supply current when the pull-up resistor is on a separate rail.
Output drive and timing at 5V
Each open-drain output sinks 12 mA at a low logic level — enough to drive a standard TTL load or an LED directly. The high-level current is listed as '-' because the open-drain structure does not source current; the external pull-up handles that. Propagation delay is 7.5 ns at 5V with a 50 pF load, which keeps the gate fast enough for most 10-20 MHz clock and data lines without adding significant skew. The input logic-low threshold spans 0.1V to 0.55V across the supply range, meaning a 0V to 0.55V signal is reliably read as low. This gives good noise margin on the low side, especially at lower supply voltages where the threshold scales proportionally.