Active 74LS dual JK flip-flop — timing and BOM fit
The SN74LS73AD is an active-production dual JK flip-flop from Texas Instruments' 74LS low-power Schottky family, clocked at 45 MHz with a 20 ns max propagation delay into 15 pF at 5 V. That 20 ns window sets the timing margin for a synchronous design — the clock-to-Q delay plus setup time on the next stage must close within one clock period. At 45 MHz the period is roughly 22 ns, leaving just 2 ns of slack before the output misses the next edge.
The 6 mA quiescent current is the idle draw; the output stage can source 400 µA and sink 8 mA per pin, enough to drive one or two standard TTL loads but not a high-fanout bus without buffering.
14-SOIC surface-mount — board integration note
Housed in a 14-SOIC package (3.90 mm body width, 0.154-inch pitch), the SN74LS73AD sits on a standard SOIC-14 footprint shared with dozens of logic ICs. The supplier device package is 14-SOIC, so the land pattern matches JEDEC MS-012 — no special copper pad or thermal management required for a 6 mA part. Tube shipment means the parts arrive in anti-static tubes; for reeled volume the order code may differ.
RoHS3 compliant — regulatory acceptance
Texas Instruments lists the SN74LS73AD as ROHS3 Compliant, covering the full RoHS exemption set including lead in solder for high-reliability applications.