5V bus buffer with 3-state control
The SN74LS244N is a dual 4-bit buffer with non-inverting outputs and 3-state control — two independent enable pins let you gate each 4-bit bank separately, which is the usual pattern for driving a shared data bus where only one source talks at a time.
Package and board-fit reality
It ships in a 20-pin DIP (0.300" body width, 7.62 mm row spacing) with through-hole leads — the 20-PDIP footprint is a standard 0.100" pitch, so it drops into any socket or plated-through hole pattern that matches the 20-pin DIP layout. The 3-state outputs mean the buffer can be put into high-impedance mode when the enable pin is deasserted — critical for shared bus architectures where multiple devices share the same data lines and only one is allowed to drive at a time.