Dual 4-input AND gate in a 14-pin DIP
The SN74LS21N: It integrates two independent AND gates, each with four inputs, in a single 14-pin plastic DIP (0.300" body width) for through-hole assembly.
20 ns propagation delay at 5 V, 15 pF
Maximum propagation delay is 20 ns at 5 V supply and 15 pF load capacitance. This sets the timing floor for the signal path — at 5 V the gate toggles in under 20 ns, which is fast enough for most 5 V control logic but not for high-speed synchronous buses above 25 MHz. Output drive capability is 400 µA sourcing (logic high) and 8 mA sinking (logic low). The asymmetric drive means the gate can sink more current than it sources — common in TTL — so downstream loads should be designed to be driven low rather than high where possible. Input logic thresholds are 0.8 V maximum for a low and 2.0 V minimum for a high, compatible with standard 5 V TTL levels. The 0.8 V low threshold gives noise margin against ground bounce on a shared backplane.
Active production, ROHS3 compliant
ROHS3 compliant — no restricted substances above threshold limits. No additional compliance documentation (REACH, UL, IEC) is listed on the product record, so the standard TI declaration of conformity applies.