Quad non-inverting buffer with tri-state — 74LS family, 5 V only
The SN74LS125ADBR: This part is suited for bus-oriented systems where individual output lines need to be disabled without affecting the rest of the bus — common in memory address decoding, peripheral select lines, and shared data buses in 5 V TTL environments.
Output drive and fan-out — what the 2.6 mA / 24 mA numbers mean
Output current: 2.6 mA source, 24 mA sink. The 3-state control allows multiple outputs to share a line without contention.
Package and footprint — 14-SSOP surface mount
The SSOP footprint is smaller than a standard SOIC, so verify the land pattern matches your PCB layout — it is not pin-compatible with SOIC-14 without a pad adjustment.
This makes it suitable for new designs requiring a standard 74LS logic buffer in a commercial temperature range.
