Triple 3-input AND gate in 14-SOIC – BOM-fit for 5V logic systems
The SN74LS11DR is a Texas Instruments 74LS-series triple 3-input AND gate in a 14-SOIC surface-mount package. It integrates three independent AND gates, each with three inputs, on a single chip – a compact solution for gating three separate 5V logic signals in a 14-pin footprint. Supply range is 4.75V to 5.25V, matching standard TTL rails.
DC and AC parametrics – what the numbers mean for your timing and drive budget
Input logic-low threshold is 0.8V max, logic-high is 2V min – standard TTL-compatible levels that interface directly with other 74LS or 74HCT devices without level translation. Quiescent current is 3.6 mA max – the total supply draw for all three gates at idle. Output drive capability is 400 µA sourcing and 8 mA sinking, sufficient for driving one or two standard TTL loads per output. Maximum propagation delay is 20 ns at 5V supply with a 15 pF load – this sets the data-rate ceiling. For a clocked system, the gate's delay adds to the combinational path; budget at least 20 ns per stage in the timing analysis.
Package, mounting, and supply format
The 14-SOIC package (3.90 mm body width) is a common surface-mount footprint, compatible with standard SOIC-14 land patterns.