Dual JK flip-flop, 45 MHz ceiling, 20 ns propagation delay
The SN74LS112AN is a dual 1-bit JK flip-flop from TI's 74LS Schottky-clamped bipolar family, clocked at 45 MHz maximum with a 20 ns propagation delay into 15 pF at 5 V. The negative-edge trigger and complementary outputs make it a direct fit for synchronous counters, shift registers, and frequency dividers where the 74LS logic level and 5 V rail are already established on the board.
Supply, drive, and temperature envelope
Runs on a 4.75 V to 5.25 V supply — the classic 5 V ±5 % TTL rail — and draws 6 mA quiescent per device. Outputs source 400 µA and sink 8 mA, enough to drive one or two standard 74LS gate inputs directly without a buffer. Rated for 0 °C to 70 °C ambient, the commercial temperature grade covers indoor equipment, bench instruments, and office-environment logic boards. The 16-pin DIP (0.300″ body, 7.62 mm row spacing) is a through-hole package that hand-assembles or wave-solders without reflow profiling.
Active lifecycle and sourcing posture
Sourced through independent distribution channels and quoted to order against the BOM quantity. Availability and current pricing are confirmed at RFQ time; no stock-holding claim is made here.