Open-collector AND gate for wired-OR and level-shifting
The SN74LS09D is a quad 2-input AND gate from the 74LS low-power Schottky family, with open-collector outputs. The open-collector stage sinks up to 8 mA per output (the '-, 8mA' figure in the spec table) but cannot source current — this means each output must be pulled up to the desired logic-high voltage through an external resistor. Typical uses include driving a wired-OR interrupt bus where multiple gates share a common pull-up, or level-shifting a 5 V logic signal to a higher-voltage rail (up to the breakdown voltage of the output transistor, typically 15 V for 74LS).
Propagation delay and timing budget
Maximum propagation delay is 35 ns at 5 V supply with a 15 pF load. This is the time from any input crossing the 1.5 V threshold to the output reaching 50% of its final swing. For a bus running at 10 MHz (100 ns period), 35 ns eats over a third of the cycle — budget this into the setup-and-hold margin if the gate sits in a critical timing path. The 74LS series is faster than the original 74 TTL (typically 10 ns vs 15 ns per gate) but slower than 74ALS or 74F.
Supply and temperature: 5 V TTL, commercial grade
The part draws its supply current from the VCC pin; typical ICC for the 74LS09 is about 6 mA per package (all gates switching). Input logic levels are TTL-compatible: low at 0.8 V max, high at 2 V min.
Package and board fit: 14-SOIC
The supplier device package is 14-SOIC — standard footprint, no thermal pad. The tube packaging means parts ship in anti-static tubes of 50 or 100, not tape-and-reel; if your pick-and-place line expects reeled parts, confirm the tube-to-reel transfer or order a reeled variant (the 'D' suffix typically indicates SOIC, but the 'R' suffix would indicate tape-and-reel).