Six inverters in a single DIP — the 74LS workhorse
The SN74LS04N packs six independent inverter gates into a single 14-pin DIP, each with one input and one inverting output. This is the classic 74LS hex inverter — a staple for signal conditioning, oscillator loops, and logic-level inversion in 5V TTL systems. Supply range is 4.75V to 5.25V, the standard TTL rail.
Each output can source 400 µA and sink 8 mA. The sink capability is the stronger side — enough to drive a standard TTL input or a low-power LED indicator, but not a relay coil or high-current load without a buffer transistor. Maximum propagation delay is 15 ns at 5V supply with a 15 pF load. This sets the timing budget for cascaded stages — six inverters in series add up to 90 ns of delay, which matters for race conditions in feedback loops or clock distribution. Input logic thresholds are 0.8V low and 2V high — standard 74LS levels. The 0.8V low threshold means a 0.4V noise margin below ground-referenced signals; the 2V high threshold leaves 0.7V margin above the 2.7V minimum TTL high output.
The 14-DIP through-hole package (0.300-inch row spacing) is a legacy footprint that remains widely supported. No board spin is needed for existing designs that already use this package.