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Texas Instruments SN74HCT04N — Analog & Data Acquisition

SN74HCT04N Texas Instruments 74HCT Hex Inverter, 14-DIP

MPNSN74HCT04N
End of Life

Texas Instruments 74HCT series hex inverter, SN74HCT04N, 6 circuits, 1-input, 14-DIP (0.300", 7.62mm), through hole, 4.5V-5.5V supply, -40°C to 85°C.

$0.68Ref. price · indicative, final on quote
Packaging14-DIP (0.300", 7.62mm)
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

SN74HCT04N Technical Specifications
ParameterValue
Series74HCT
Logic typeInverter
Mounting typeThrough Hole
Voltage4.5V ~ 5.5V
Current - quiescent2 µA
Current - output high, low4mA, 4mA
Number of inputs1
Operating temperature-40°C ~ 85°C
PackageTube
Case14-DIP (0.300\", 7.62mm)
Number of circuits6
Input logic level - low0.8V
Input logic level - high2V
Max propagation delay @ v, max CL18ns @ 5.5V, 50pF

Product details

14-pin DIP integration

The SN74HCT04N is a hex inverter from Texas Instruments' 74HCT family, packaged in a 14-DIP (0.300", 7.62mm) through-hole body. The 14-PDIP footprint mates with standard 0.100-inch pitch sockets or solder pads, making it a direct drop-in for breadboard prototyping or legacy PCB designs that avoid surface-mount assembly. The 2 µA max quiescent current keeps the power budget tight in always-on or battery-backed sections of the board.

Switching and drive margins

For a 5 V rail, the 18 ns delay limits the toggle frequency to roughly 28 MHz before the output fails to settle within the next clock edge. Output drive capability is symmetrical at 4 mA source and 4 mA sink, sufficient to drive one or two standard LSTTL loads or the input of a downstream 74HCT gate. The input logic thresholds — 0.8 V low and 2 V high — are TTL-compatible, so the part interfaces directly with 5 V TTL logic without external level translation.