Automotive-grade XOR gate in a 14-SOIC footprint
21 ns propagation delay — timing budget for the bus
The maximum propagation delay is 21 ns at 6V supply with a 50 pF load. That is the figure to use when calculating worst-case signal propagation through a chain of gates — for example, in a parity-check or address-decoder path. At lower supply voltages the delay increases, so if the design runs at 3.3V, budget more margin. The 5.2 mA output drive (both high and low) is typical for HC logic and drives one or two standard CMOS loads without buffering.
The Q1 suffix signals automotive qualification per AEC-Q100, which includes extended temperature testing, reliability stress, and lot traceability. For a production BOM in a vehicle ECU, this is the gate that passes the PPAP audit — the commercial-grade 74HC86 without the Q1 suffix does not.