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Texas Instruments SN74HC32PW — Analog & Data Acquisition

SN74HC32PW Texas Instruments 74HC Quad OR Gate, 14-TSSOP

MPNSN74HC32PW
End of Life

Texas Instruments 74HC series quad 2-input OR gate, SN74HC32PW, 14-TSSOP package, 2V to 6V supply, 17ns propagation delay at 6V, -40°C to 85°C operating temperature.

$1.16Ref. price · indicative, final on quote
Packaging14-TSSOP (0.173", 4.40mm Width)
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
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Specifications

SN74HC32PW Technical Specifications
ParameterValue
Series74HC
Logic typeOR Gate
Mounting typeSurface Mount
Voltage2V ~ 6V
Current - quiescent2 µA
Current - output high, low5.2mA, 5.2mA
Number of inputs2
Operating temperature-40°C ~ 85°C
PackageTube
Case14-TSSOP (0.173\", 4.40mm Width)
Number of circuits4
Input logic level - low0.5V ~ 1.8V
Input logic level - high1.5V ~ 4.2V
Max propagation delay @ v, max CL17ns @ 6V, 50pF

Product details

Active lifecycle — no end-of-life signal on this 74HC OR gate

The 74HC series is a mature logic family with broad second-source coverage, but the SN74HC32PW itself has no official pin-compatible successor from TI — the BOM position stays stable as long as the package and supply voltage match.

Quad 2-input OR gate — what the logic function means for your BOM

The SN74HC32PW contains four independent 2-input OR gates in a single 14-TSSOP package. Each gate performs the Boolean OR operation: the output is high when at least one input is high. This is a fundamental building block for glue logic, signal gating, and combinatorial control paths. With four circuits on one die, the part replaces four discrete OR-gate packages or consolidates a PAL/GAL macrocell in low-density designs.

Supply voltage and temperature grade — where this part fits

The input logic levels scale with Vcc: low threshold is 0.5V to 1.8V, high threshold is 1.5V to 4.2V, so the gate interprets standard CMOS and TTL levels correctly across the supply range. The 2 µA max quiescent current means the part adds negligible standby draw in battery-powered or always-on subsystems.

Propagation delay and output drive — timing budget for the signal path

Maximum propagation delay is 17 ns at 6V supply with a 50 pF load. At 5V the delay is typically 12-14 ns, which sets the maximum toggle rate around 30-40 MHz in a clean layout — enough for SPI clock gating, address decoding, or reset sequencing, but not for high-speed parallel buses. The symmetrical drive strength means rise and fall times are balanced, reducing skew in clock-gating applications.

Package and compliance — board-fit and regulatory readiness

The 14-TSSOP package (supplier device package 14-TSSOP) has a 4.40 mm body width and 0.65 mm pin pitch. The footprint matches standard TSSOP-14 land patterns; the 0.173-inch (4.40 mm) width is narrower than SOIC-14 (3.91 mm vs 6.00 mm), so a layout change is required when migrating from SOIC to TSSOP. ROHS3 compliant per TI's certification, with no restricted substances above the threshold.

Frequently asked questions

What is the closest functional second-source to SN74HC32PW?

The SN74HC27APWR is a 74HC-series NOR gate in the same 14-TSSOP package, but it is a 3-input NOR (not 2-input OR) with three circuits instead of four. It will not drop into the same logic function without a board redesign.

What compliance documentation does Texas Instruments provide for SN74HC32PW?

The part is ROHS3 compliant.