Quad buffer with 3-state outputs in 14-SSOP
The Texas Instruments SN74HC125DBR is a 74HC-series CMOS logic buffer with four independent non-inverting channels, each featuring a 3-state output controlled by an active-low output-enable pin. Typical applications include bus isolation, memory address latching, and general-purpose line driving where a high-impedance output state is needed to avoid bus contention.
Each of the four buffers can source or sink 7.8mA, which is typical for standard 74HC logic. This limits fan-out to about 10 LSTTL loads or 40 74HC inputs per channel. If you need to drive a heavier bus (e.g., multiple memory chips or a long backplane trace), plan on using the output to enable a higher-drive transceiver or buffer the signal with a discrete transistor. The 3-state output lets you float the line when the output-enable pin is high, which is essential for shared data buses where multiple devices take turns driving.
The 2V to 6V supply range covers the two most common logic rails in industrial and consumer designs: 3.3V and 5V. No level translator needed if the rest of the bus runs at the same voltage.